The present invention relates to an input initial stage circuit for a semiconductor memory, and more specifically to an input initial stage circuit so configured to prevent malfunction of an internal circuit in a semiconductor memory, attributable to a parasite signal, when an external clock having a slow voltage transition is applied.
Recently, with an elevated performance of a system such as a computer operating in a digital manner, a semiconductor memory used in the digital system is required to have a high operating frequency. At present, a dominant semiconductor memory adapted for a high speed operation is comprised of a synchronous DRAM (dynamic random access memory) having an internal address count-up function, a burst operation function and an operation mode setting function.
Here, the burst operation function is that, in an operation of the synchronous DRAM, when an address is designated from an external, data of the number of bursts designated in the operation mode is continuously read or written from the value of the address. In addition, the internal address count-up function is that, in the burst operation, an internal address counter counts up from the initially set address in synchronism with a clock supplied from an external, to increment the address value by the number corresponding to the number of bursts designated in the operation mode. Furthermore, the operation mode setting function is to set the number of bursts, to set an output data delay, and to set the manner of counting up the address, in response to an external command, in the operation of the synchronous DRAM.
A basic construction of the prior art synchronous DRAM having the internal address count-up function, the burst operation function and the operation mode setting function, will be described with reference to FIG. 4, which is a block diagram illustrating a basic construction of the synchronous DRAM in accordance with the present invention. The shown synchronous DRAM comprises an input initial stage circuit 11, a flipflop (F/F) circuit 12, a logic decoder 13, an address counter 14, a memory controller 15 and a memory cell array 16, which are coupled as shown.
In the prior art synchronous DRAM, the input initial stage circuit 11 receives an external clock CLK and generates an internal clock "INTERNAL CLOCK". The internal clock is supplied to the flipflop circuit 12 and the address counter 14. The flipflop circuit 12 latches and outputs external commands .phi.1, .phi.2 and .phi.3 in response to the internal clock. The logic decoder 13 receives the external commands outputted from the flipflop circuit 12, and outputs various instructions including a read instruction "READ", a write instruction "WRITE", and a number-of-bursts instruction "NUMBER OF BURSTS". The address counter 14 receives an external address .phi.4 and counts up the internal clock to output an address "ADDRESS" to the memory controller 15. The memory controller 15 receives the address from the address counter 14 and the read instruction "READ", the write instruction "WRITE" and the number-of-bursts instruction "NUMBER OF BURSTS" from the logic decoder, and controls the memory cell array 16 to execute a reading or writing of the designated number of bursts from the designated address. Thus, under control of the memory cell controller 15, data is read from or written into the memory cell array 16 in a burst mode.
A prior art input initial stage circuit is constituted of an inverter 21, as shown in FIG. 5, which inverts an input signal to output an amplified inverted signal as an output signal.
In the above mentioned semiconductor memory, with an elevated operation speed of the semiconductor memory, the input initial stage circuit is constituted of a circuit which can operate with a high speed of for example about Ins or less.
However, a memory simple testing apparatus used in a fabricating process for sorting and evaluating the semiconductor memories cannot generate a test signal meeting with the high speed operation, and therefore, a test signal having a slow voltage transition is used for testing the semiconductor memory.
If there was used the testing apparatus generating a test signal having a voltage transition which is slow in comparison with the operating speed of the input initial stage circuit, the input initial stage circuit generates a parasite signal composed of an unexpected short pulse, which causes a malfunction in an internal circuit of the semiconductor memory. As a result, it become impossible to verify whether or not a normal operation is executed.
Referring to FIG. 6, there is shown a timing chart illustrating a change of an input signal and an output signal of the prior art input initial stage circuit. In the input initial stage circuit constituted of the inverter 21 as shown in FIG. 5, a threshold value when an input level changes from a low level to a high level is the same as that when the input level changes from the high level to the low level. This threshold is indicated with "S" in FIG. 6.
As shown in FIG. 6, when the input signal applied to the inverter 21 monotonously increases as indicated with "A", an output signal "B" of the inverter is constant at a high level unless the level of the input signal "A" exceeds the threshold "S". When the level of the input signal "A" exceeds the threshold "S", an electric current flows in the inside of the inverter, so that the output voltage "B" of the inverter drops. At this time, the threshold of the inverter becomes high because of a power supply voltage variation in the inside of the circuit. Therefore, at a next moment, the electric current does not flow in the inverter, so that the output voltage "B" of the inverter elevates again. Then, because the electric current does not flow in the inverter, the threshold of the inverter becomes low, with the result that the electric current flows again in the inverter, and therefore, the output voltage "B" of the inverter drops again.
This phenomenon occurs repeatedly, so that the output voltage "B" of the inverter vigorously varies up and down to generate short pulses as designated with "B1" and "B2" in FIG. 6, and simultaneously, the threshold of the inverter correspondingly varies.
After this variation is repeated some times, the level of the input signal "A" becomes ceaselessly higher than the threshold "S", with the result that the output voltage "B" of the inverter is stabilized at a low level.
As mentioned above, when the voltage transition of the input signal used for testing the semiconductor memory is considerably slower than the operation speed of the input initial stage circuit of the semiconductor memory, the threshold of the input initial stage circuit varies up and down at a rate higher than the speed of the voltage transition of the input signal, because of an internal power supply voltage variation and others. As a result, in response to the monotonous change of the input signal (clock) in a single cycle, the input initial stage circuit cannot generate the output signal which correctly reflects the change of the input level, but generates a parasite signal composed of for example a plurality of repeated short pulses. Therefore, the address counter receiving the output of the input initial stage circuit erroneously counts up to consequentially generate an erroneous address, with the result that the reading operation or the writing operation of the semiconductor memory is not performed normally.